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high performance ism band ook/fsk transmitter ic adf7901 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features single-chip, low power uhf transmitter 369.5 mhz to 395.9 mhz frequency operation using fractional-n pll and fully integrated vco 3.0 v supply voltage data rates up to 50 kbps supported low current consumption 26 ma at 12 dbm output at 384 mhz power-down mode (<1 a) 24-lead tssop general description the adf7901 is a low power ook/fsk uhf transmitter designed for use in rf remote control devices. it is capable of frequency shift keying (fsk) modulation on eight different channels, selectable by three external control lines. ook modulation is performed by modulating the pa control line. the on-chip vco operates at 2 the output frequency. the division by 2 at the output of the vco reduces the amount of pa feedthrough. as a result, ook modulation depths of greater than 50 db are easily achievable. the fsk_adj and ask_adj resistors can be adjusted in the system to optimize output power for each modulation scheme. an additional 1.5 db of output power is provided for the lower bank of channels to adjust for antenna performance. the ce line allows the transmitter to be powered down completely. in this mode, the leakage current is typically 0.1 a. functional block diagram r = 1 fsk dv dd t x data ce d gnd fsk1 ook_sel rf out rf gnd v dd r set osc2 c vco c reg2 pa_en rset_fsk rset_ook osc1 pa c reg2 c reg1 ldo regulator 1 ldo regulator 2 pdf charge pump ? fractional n - fsk2 fsk3 channel select vco 05349-001 figure 1.
adf7901 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 8 circuit description........................................................................... 9 loop filter ..................................................................................... 9 channel frequencies..................................................................... 9 layout guidelines....................................................................... 10 decoupling.............................................................................. 10 regulator stability .................................................................. 10 grounding............................................................................... 10 supply ...................................................................................... 10 digital lines............................................................................ 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 3/06rev. 0 to rev. a added crystal esr parameter ........................................................ 4 change to figure 8 ......................................................................... 10 updated outline dimensions ....................................................... 11 changes to ordering guide .......................................................... 11 3/05revision 0: initial version
adf7901 rev. a| page 3 of 12 specifications v dd =3.0 v; gnd = 0 v; t a = t min to t max , unless otherwise noted. typical specifications, t a = 25c. 1 table 1. parameter min typ max unit comments/conditions rf characteristics output frequency ranges channel 1 369.5 mhz channel 2 371.1 mhz channel 3 375.3 mhz channel 4 376.9 mhz channel 5 384.0 mhz channel 6 388.3 mhz channel 7 391.5 mhz channel 8 394.3 mhz channel 9 395.9 mhz phase frequency detector frequency 9.8304 mhz transmission parameters transmit rate fsk 50 kbps ook 50 kbps frequency shift keying fsk separation 2 ?34.8 khz data = 1 +34.8 khz data = 0 on/off keying modulation depth 3 83 db output power = 12 dbm output power min/max range 4 15 dbm f out 384 mhz 10 12 dbm f out > 384 mhz 7 10.5 dbm occupied 20 db bw ook at 1 kbps 28 461.9 khz fsk (pa off/on) at10 hz 5 26 461.9 khz logic inputs v inh , input high voltage 2.124 v v inl , input low voltage 0.2 v dd v i inh /i inl , input current 1 a c in , input capacitance 10 pf power supplies voltage supply dv dd 3.0 v transmit current consumption 369.5 mhz to 376.9 mhz at 12 dbm 26 ma 384 mhz at +12 dbm 26 ma 388.3 mhz to 395.9 mhz at 10.5 dbm 21 ma 384 mhz at 5 dbm 17 ma power-down mode low power sleep mode 6 0.2 1 a
adf7901 rev. a | page 4 of 12 parameter min typ max unit comments/conditions phase-locked loop vco gain 30 mhz/v at 384 mhz spurious 3, 7 100 khz loop bw integer boundary C45 ?23 dbc reference ?70 ?23 dbc harmonics 3 second harmonic v dd = 3.0 v ?24 ?21 dbc third harmonic v dd = 3.0 v ?14 ?11 dbc all other harmonics ?18 dbc reference input crystal reference 9.8304 mhz crystal esr 8 80 power amplifier pa output impedance 97 + 6.4 pf at 384 mhz timing information crystal oscillator to pll lock 3 2 3 ms pa enable to pa readyCpll settle 9 100 250 s temperature range (t a ) 0 50 c 1 operating temperature range is 0c to 50c. 2 frequency deviation = 58 (9.8304 mhz)/2 14 . error in the crystal is reflected in variation in the desired deviation. 3 not production tested; based on characterization. 4 the output power can be varied in both ask/fsk mode by altering the relevant external resistor. 5 measured using spectrum an alyzer, 1 mhz span, 100 khz r bw, maximum hold enabled. 6 maximum power-down current specificatio n applies for the osc2 pin grounded. 7 measured >461.9 khz away from channel. 8 maximum recommended crystal esr. the crystal oscillator works with crystals with higher esr, but this results in longer power- up times. 9 this specification refers to the time taken for the pll to regain lock after the pa has been enabled. the pa is should only be enabled after the pll has settled to the correct frequency.
adf7901 rev. a| page 5 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. 1 table 2. parameter value v dd to gnd 2 ?0.3 v to +4.0 v rfvdd to gnd ?0.3 v to +4.0 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) 0c to 50c storage temperature range ?65c to +125c maximum junction temperature 125c tssop ja thermal impedance 150.4c/w lead temperature, soldering vapor phase (60 sec) 235c infrared (15 sec) 240c 1 this device is a high performance, rf-integrated circuit with an esd rating of <1 kv. it is esd sensitive. take proper precautions for handling and assembly. 2 gnd = rf gnd = d gnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adf7901 rev. a | page 6 of 12 pin configuration and fu nction descriptions top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 adf7901 d gnd nc txdata fsk3 r set cp out fsk1 ce ook _ sel osc2 osc1 rset_ook c reg1 c vco vco in dv dd rf gnd rf out fsk2 dv dd pa_en c reg2 d gnd rset_fsk 05349-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic function 1 dv dd positive supply for the digital circuitry. this must be 3. 0 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 2 c reg1 a 2.2 f capacitor should be added at creg1 to reduce regulator noise and improve stability. a reduced capacitor improves regulator power-on time but can cause higher spurious. 3 cp out charge pump output. this output genera tes current pulses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 4 txdata digital fsk data to be tr ansmitted is inputted on this pin. 5 d gnd ground for digital section. 6 nc no connect. 7 d gnd ground for digital section. 8 osc1 the reference crystal should be connected between this pin and the osc2 pin. the necessary crystal load capacitor should be tied between this pin and ground. 9 osc2 the reference crystal should be connected between this pin and the osc1 pin. the necessary crystal load capacitor should be tied between this pin and ground. a tcxo or external square wave can also be connected to this pin, with osc1 left floating. a dc-blocking capacitor (4.7 nf is adequate) should be pl aced between the tcxo output and osc2 pin. when not using an external regulator, a 1 m resistor ca n be tied between the osc2 pin and ground to meet the power-down current specification of 1 a. 10 ook_sel a high on this pin selects operat ion in ook mode at 384 mhz when ce is high. 11 fsk1 fsk channel select pin. this represents the lsb of the channel select pins. 12 fsk2 fsk channel select pin. 13 fsk3 fsk channel select pin. 14 ce bringing ce low puts the adf7901 into power-down, drawing <1 a of current. 15 rset_ook the value of this resistor sets the output power for data = 1 in ook mode. a resistor of 3.6 k provides the maximum output power. increasing the resistor reduces th e power and the current consumption. a lower resistor value than 3.6 k can be used to increase the power to a maximum of 14 dbm. the pa does not operate efficiently in this mode. 16 rset_fsk the value of this resistor sets the output power in fs k mode. a resistor of 3.6 k provides maximum output power. increasing the resistor reduces the power and the current consumption. a resistor value lower than 3.6 k can be used to increase the power to a maximum of 14 db m. the pa does not operate efficiently in this mode. 17 c vco a 22 nf capacitor should be tied between the c vco and c reg2 pins. this line should run underneath the adf7901. the capacitor is necessary to ensure stable vco operation. 18 vco in the tuning voltage on this pin deter mines the output frequency of the volt age controlled oscillator (vco). the higher the tuning voltage the higher the output frequenc y. the output of the loop filter is connected here. 19 rf gnd ground for output stage of transmitter. 20 rf out the modulated signal is available at this pin. output power levels are from C5 dbm to +12 dbm. the output should be impedance matched using suitable components to the desired load.
adf7901 rev. a| page 7 of 12 pin no. mnemonic function 21 dv dd voltage supply for vco and pa section. it should be supp lied with 3.0 v. decoupling capacitors to the ground plane should be placed as close as possible to this pin. 22 pa_en this pin is used to enable the power amplifier. it sh ould be modulated with the ook data in ook mode. in fsk mode, it should be enabled when the pll is locked. 23 r set external resistor. sets charge pump current and so me internal bias currents. use 3.6 k as default. 24 c reg2 a 2.2 f capacitor should be added at c reg2 to reduce regulator noise and improve stability. a reduced capacitor improves regulator power-on time but can cause higher spurs.
adf7901 rev. a | page 8 of 12 typical performance characteristics rset output power (dbm) 16 12 8 4 0 2 35 9 710 468 05349-004 figure 3. output power vs. r set fsk, upper fsk channels, measured into 50 output power (dbm) i dd (ma) 30 25 20 15 10 35 59 710 468 05349-005 figure 4. current consumption vs. output power, upper fsk channels, measured into 50 center 395.948 29mhz #res bw 300hz vbw 300hz span 50khz sweep 2.118 s (601 pts) mkr1 10.00khz noise ?89.55db/hz ref 15dbm avg log 10 db/ pavg w 1 s3 (f): f<50k swp s2 fs aa atten 30db rbw 300.0000000hz 1r 1 05349-006 figure 5. phase noise at channel 9 center 5.50ghz #res bw 1mhz vbw 1mhz span 10.5ghz sweep 17.52 ms (601 pts) mkr4 1.59ghz ?21.30db ref 15dbm peak log 10 db/ lgav atten 30db 1 2 3 4 marker 1 2 3 4 trace (1) (1) (1) (1) type freq freq freq freq x axis 400mhz 800mhz 1.19ghz 1.59ghz amplitude ?25.56db ?13.89db ?34.53db ?21.30db 05349-007 4r figure 6. harmonic levelsup to fourth harmonic, measured at channel 9 into 50
adf7901 rev. a| page 9 of 12 circuit description table 4. frequency (mhz) fsk3 fsk2 fsk1 ook_sel 369.5 0 0 0 0 371.1 0 0 1 0 375.3 0 1 0 0 376.9 0 1 0 0 384.0 dont care dont care dont care 1 388.3 1 0 0 0 391.5 1 0 1 0 394.3 1 1 0 0 395.9 1 1 1 0 loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. the recommended loop filter design for this circuit is 297 khz. this is based on the trade-off between attenuation of beat note spurs and the need to minimize chirp when the pa is turned on. charge pump out vco 05349-008 r2 = 6.2k c3 = 10pf c1 = 33pf c2 = 390pf r1 = 3k improved spurious performance in fsk mode can be achieved by using a narrower loop bandwidth. for a data rate of 20 kbps, a loop bandwidth of roughly 50 khz would be suitable. the following components give a loop bandwidth of 51.1 khz: c1 = 680 pf c2 = 15 nf c3 = 180 pf r1 = 510 r2 = 6.2 k adisimpll is a free software tool offered by analog devices for assistance in designing with adis frequency synthesizers and ism band transmitters. to select the correct loop filter components for use with the adf7901, open a project for the adf7012 device. then, enter the desired output carrier frequency and loop bandwidth, and use the 870 a charge pump current setting. adisimpll can be downloaded from www.analog.com. channel frequencies the nine channel frequencies listed in table 4 are obtainable from a single 9.8304 mhz crystal reference by changing the value of the n and f numbers in the fractional pll, using control lines fsk1, fsk2, and fsk3. the channel frequency is given by f channel = f ref (n + f) however, the vco is tuned to operate over a frequency range of 344 mhz to 401 mhz (typically). therefore, any channel frequency within this range can be obtained if the required reference frequency is used. the n and f numbers for each channel are listed in table 5, together with the corresponding channel frequencies for 9.8304 mhz and, for example purposes, frequencies for 10 mhz. with the 10 mhz reference, the two largest n settings give channel frequencies above the maximum vco output frequency and are therefore invalid. frequency deviation is also dependent on reference frequency. the relationship is given by f dev = 58 (9.8304 mhz)/2 14 therefore, the frequency deviation is 34.8 khz when the 9.8304 mhz reference is used and 35.4 khz when the 10 mhz reference is used. table 5. channel frequency (mhz) n f 9.8304 mhz ref 10 mhz ref 37 2406/4096 369.5 375.9 37 3073/4096 371.1 377.5 38 727/4096 375.3 381.8 38 1374/4096 376.9 383.4 39 256/4096 384.0 390.6 39 2048/4096 388.3 395 39 3381/4096 391.5 398.3 40 452/4096 394.3 n/a 40 1118/4096 395.9 n/a
adf7901 rev. a | page 10 of 12 3pf 8pf 22nh 27nh 5.6pf dv dd rf out r set 3.6k c reg2 2.2 f 22nf c vco cp out vco in vco in fsk1 fsk2 fsk3 ook_sel txdata ce 9.8304mhz 33pf 33pf gnd osc2 osc1 antenna adf7901 pa_en rset_fsk rset_ook 3.6k 3.6k c reg1 2.2 f 3pf 1.5pf 22nh 36nh matching 50 to antenna 5th-order, low-pass filter matching rf out to 50 05349-003 notes 1. decoupling capacitors have been omitted for clarity. figure 8. applications diagram for the adf7901 in a remote control system layout guidelines the layout of the board is crucial to ensuring low levels of spurious and harmonics. decoupling decoupling capacitors (high frequency 22 pf, low frequency 100 nf) should be placed as close as possible to the supply pins on the part. low size 0402 and 0603 components are recom- mended for the high frequency rejection on the supply. regulator stability a minimum of 1 f is needed on both c reg1 and c reg2 to ensure stability. an additional 22 pf capacitor can be added to reject higher frequency noise. because many of the internal blocks run off the regulator, it is critical to reduce its noise. low size 0402 and 0603 components are recommended for the high frequency rejection on the supply. grounding emphasis should be placed on grounding once the decoupling capacitors have been added. the pa stage switches currents of 15 ma in maximum power mode. this causes changes in the ground resulting in large return currents that can radiate to other parts of the board. the shortest and least obstructed ground from rf gnd back to the ground of the battery should be ensured. a 4-layer board helps, as well as flooding the top layer. the ground paths should not have any vias and should be wide tracks. supply the supply tracks can be routed through vias, because they act as free inductors and make layout easier on a 2-layer board (see the decoupling section). tracks should be wide. digital lines digital lines should contain a large resistor in series. this impedance blocks signals of many frequencies, including harmonics and the carrier frequency. long control lines can act as antennae. it can be useful to add capacitance to ground. there is some capacitance to ground provided by the lines and at the input of the digital pins.
adf7901 rev. a| page 11 of 12 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153ad figure 9. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range package description package option ADF7901BRU 0c to 50c 24-lead thin shrink small outline package (tssop) ru-24 ADF7901BRU-reel 0c to 50c 24-lead thin shrink small outline package (tssop) ru-24 ADF7901BRU-reel7 0c to 50c 24-lead thin shrink small outline package (tssop) ru-24 ADF7901BRUz 1 0c to 50c 24-lead thin shrink small outline package (tssop) ru-24 ADF7901BRUz-rl 1 0c to 50c 24-lead thin shrink small outline package (tssop) ru-24 ADF7901BRUz-rl7 1 0c to 50c 24-lead thin shrink small outline package (tssop) ru-24 eval-adf7901eb evaluation board 1 z = pb-free part.
adf7901 rev. a | page 12 of 12 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05349-0-3/06(a)

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